The present invention relates to a semiconductor device and its manufacturing technology and, more particularly, to a semiconductor device including a plurality of capacitive elements and a technology effective when applied to its manufacture.
In Japanese patent laid-open No. 2003-60042 (patent document 1), a technology is described, which forms a capacitive element (capacitor) by laminating it over a semiconductor substrate. Specifically, a structure is disclosed, which is formed by laminating a MOS (Metal Oxide Semiconductor) capacitor including a well (first electrode) formed in the semiconductor substrate and a second electrode including a polysilicon film formed over the well via an insulating film and a PIP (Polysilicon Insulator Polysilicon) capacitor including the second electrode and a third electrode including a polysilicon film formed over the second electrode via an insulating film.